1. Field of the Invention
The present invention relates generally to memory cache, and in particular, to a method, apparatus, and article of manufacture for a low-power and radiation tolerant cache design.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by reference numbers enclosed in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
Nearly all modern microprocessors incorporate memory caches for both data and instructions. These caches take advantage of the strong correlations in both space and time between multiple accesses to main memory. Storing a copy of the current working set of both instructions and data in the processor results in an enormous reduction of processor to memory I/O which in turn leads to substantial reduction in the average memory access time and the average memory power consumption. Unfortunately, caches are highly customizable, and the design space is vast. It follows that when designing a cutting edge low-power microprocessor, the cache architecture and size are paramount design concerns. Moreover, as caches tend to occupy a substantial portion of the die, designing towards the additional goal of robust radiation hardened chips only increases the importance of the cache design. To date that has been widely overlooked in both industry and academia.